Although the reasons are numerous, including increased energy efficiency and capacity, it has become necessary to manufacture integrated circuits continuously smaller and with denser feature profiles. It is necessary, therefore, that the constituent features that form the integrated circuit, e.g., interconnect lines and electrical devices, also continue to decrease in size to accommodate these continuing demands. This trend of decreasing feature size is evident, for example, in memory circuits and devices such as dynamic random access memory (“DRAM”), logic gate arrays and non-volatile memory devices such as flash memory.
As an example, a DRAM device can comprise millions of identical circuit elements known as memory cells. Each memory cell may include two electrical devices, a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one binary bit of data. A bit of data can be written to a memory cell through the access transistor and read by sensing charge on the storage capacitor. In another example, flash memory cells contain floating gate field effect transistors capable of holding a charge. Flash memory cell data is determined by the presence or absence of a charge on the floating gate. Flash memory cells may be arranged in different architecture configurations, such as either a “NOR” architecture where each memory cell is coupled with a bit line or a “NAND” architecture where memory cells are aligned in a “string” of cells such that activation of the entire bit line is necessary for access of the data.
As is evident from the above examples, memory devices typically include large patterns or arrays of electrical devices and device interconnecting conductors. As these features continue to decrease in size, increasingly greater demands are placed on the manufacturing techniques used to form these features. Features are commonly defined using the term “pitch,” where the pitch of a pattern is the distance between two identical points within a repeating pattern, such as features in arrays. Thus, pitch can be described as the sum of the width of a feature and the width of the neighboring space on one side of the feature which separates the feature from the nearest neighboring feature.
In integrated circuits, the smallest or minimum feature dimension of a particular circuit design or masking scheme, such as a word line, is known as the critical dimension (“CD”). The CD can be described as the pitch or the measurement of the smallest feature capable of being formed by the design or scheme. For instance, with the continued scaling of flash memory technology, controlling the CD of certain structures during fabrication, such as shallow trench isolation (“STI”) structures, is critical to this continued scaling. As these device elements are reduced in size, the difficulty of patterning them increases.
One of the primary methods of patterning features during integrated circuit manufacture is photolithography. However, photolithography techniques have inherent limitations due to optical and radiation wave length characteristics such that these limitations inhibit the use of photolithography to directly form the reduced features. For example, certain photoresist materials act in response to particular wavelengths of light. This selectivity to specific light wavelengths limits individual photolithography methods to a minimum pitch below which each particular photolithography technique can not reliably form features. As such, the pitch capable of being produced through photolithography becomes an impediment to continuous feature size reduction.
One method of reducing the pitch size, and thereby extending the present capabilities of photolithography, is know as pitch doubling or pitch multiplication (see e.g., U.S. Pat. No. 5,328,810 issued to Lowery et. al.). During this process, the pitch is actually decreased, thereby increasing the number of features which can be fabricated in a given area. One technique used to multiply pitch is to use features such as side wall spacers to create smaller patterns than present lithography techniques are capable of producing.
Accordingly, there is a need for methods for operational control of critical dimension and process variations during size-reduced feature fabrication in integrated circuit production.
It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details embodiments of the invention.